Before synthesis, chip designers used to implement all aspects of chip design by hand. This included combinational logic implementation, storage elements such as SRAMs, flip-flops and latches. Netlist as well as place-and-route were also done fairly manually. High-level design implementations, either in C, Verilog or another high-level language, were manually translated into gates.
When synthesis arrived, chip design moved up to a higher level of abstraction, implementing designs in HDL (VHDL or Verilog), with synthesis translating HDL into logic gates and storage elements, even inferring SRAM storage. This eliminated much manual labor of chip design. Synthesis also optimized paths well and enabled engineers to work on much larger designs, which are still growing at Moore’s self-fulfilling-prophecy pace.
However, even today synthesis limits the style of designs that engineers are able to create. Synthesis performs well for certain kinds of design styles, while not supporting others. While HDL is capable of describing all kinds of designs, logic and storage structures, only a subset of these is synthesizable. Designers must be cautious about what they feed into synthesis tools, to ensure functionally correct results. Otherwise, many kinds of problems can result, which are not only incorrect, but can also appear to work correctly, but instead be intermittently incorrect at random intervals.
Design Style Synthesis Supports
The main design style which today’s mainstream synthesis products by companies such as Synopsys, Cadence, and various FPGA vendors support is synchronous single-phase of clock flip-flop style. This singular style is the simplest for synthesis to handle and is the most productive. When designing a component which uses a single clock with inputs and outputs synchronous to the same clock, a designer can move at maximum speed of productivity with minimal concern besides correct functionality.
This design style contains asynchronous logic only between flip-flops. Reset is handled carefully per FPGA-vendor of ASIC library vendor recommendations of being synchronous or asynchronous. Synthesis handles this design style well, providing additional capabilities such as automatic pipelining of logic across flip-flop stages.
However, any deviation from that singular synchronous design style, slows things down because caution must be observed with more care, patience and expertise applied. The following cases require additional caution:
- multiple clock domains, where parts of the design run at one clock frequency while other parts run on one or more different clock frequencies
- multiplexing multiple input clocks down to a single output clock
Design Styles Synthesis Does Not Support
Dynamic logic, Latch-based design (such as dual-phase), Wave pipelining, Asynchronous logic, styles are not supported by the mainstream synthesis design products.